27 Jan 2021
Given:
Your simulator should support the following:
o addi, addu, sub, slt, and, ori, sll, srl beq, bne, lw, sw
o add, slti, sltu, lui, andi, or, xor, xori, j
use the sample code to follow and simulate python code that would identity and return output to user indicating:
a) Register content ($8 – $23, PC)
b) Memory content (0x2000 – 0x2050)
c) Instruction Count
d) Other helpful info (such as current instruction, etc)
pretty much just checking the op code and change in pdf file to identify different instructions and then edit the rest operation and memory part